The present disclosure relates generally to an integrated circuit (IC) device and, more particularly, a method of forming a high-k metal gate structure of an IC device.
The semiconductor industry has employed several strategies to meet the demands for decreasing sizes of integrated circuits. One such strategy is the use of high-k materials for gate dielectrics. High-k gate dielectrics include those dielectric materials having a higher dielectric constant than silicon oxide, a conventional gate dielectric. High-k gate dielectrics allow a thicker gate dielectric layer (e.g., as compared to SiO2) to provide a similar equivalent oxide thickness (EOT). The thicker layer allows for increased reliability and lower leakage currents. Recent trends in semiconductor fabrication have also employed metal gate technologies. Metal gates allow for lower resistance than conventional polysilicon gates. Metal gates may also be compatible with the underlying high-k dielectrics.
However, the fabrication processes providing for use of a high-k dielectric plus metal gate structure face challenges. “Gate-last” processes have been developed that provide for reduced risk of damage to the final gate structure, for example, during high temperature processes of forming the gate stack. A gate-last process includes the formation of a dummy polysilicon gate on a substrate, the dummy gate includes a sacrificial structure which is replaced by a metal gate structure. In a gate-last process however, several processing issues remain including, for example, those associated with a chemical mechanical polish (CMP) process and the interlayer dielectric (ILD) deposition between gates (e.g., reducing voiding).
Therefore, what is needed is an improved method of forming a gate structure.